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[Embeded-SCM Develop] cf_fp_mul_p_5_10

Description: verilog浮点乘发器，特定数据结构，指数底为10,利用pipeline-Verilog float by their hair, a specific data structure, the index for the end of October, using pipeline
Platform: | Size: 4096 | Author: 丁谨 | Hits:

[Embeded-SCM Develop] cf_fp_mul_p_8_23

Description: verilog浮点乘发器，特定数据结构，指数底为10,利用pipeline-Verilog float by their hair, a specific data structure, the index for the end of October, using pipeline
Platform: | Size: 6144 | Author: 丁谨 | Hits:

[VHDL-FPGA-Verilog] pipe

Description: verilog编写的流水线模块-Verilog modules prepared by the Pipeline
Platform: | Size: 5120 | Author: 刘陆陆 | Hits:

[SCSI-ASPI] dlx_verilog

Description: 这是我个人写的DLX处理器流水线的Verilog代码，在ModelSim中仿真通过，并且在ISE中能综合！即可以下载到FPGA中运行指令，指令可以根据需要定义，也可和相应的编译器配合使用，这里给学习流水线和Verilog的朋友共享。-This is my personal wrote DLX pipeline processor Verilog code, adopted in the ModelSim simulation and can be integrated in the ISE! That can be downloaded to the FPGA to run commands, instructions can be defined as needed, but also the compiler and the corresponding use, where to learn lines and Verilog friends sharing.
Platform: | Size: 9216 | Author: 李乔 | Hits:

[VHDL-FPGA-Verilog] FIFO_8_8

Description: FIFO先进先出队列，一种缓存、或一种管道、设备、接口（Verilog HDL程序,内附说明）-FIFO FIFO queue, a cache, or a pipeline, equipment, Interface (Verilog HDL program, containing a note)
Platform: | Size: 5120 | Author: 镜子 | Hits:

[VHDL-FPGA-Verilog] add

Description: 流水线乘法器与加法器 开发环境：Modelsim（verilog hdl）-Multiplier and adder pipeline development environment: Modelsim (verilog hdl)
Platform: | Size: 1024 | Author: 来法旧佛 | Hits:

[ARM-PowerPC-ColdFire-MIPS] MIPS

Description: 带分支预测的MIPS流水线的verilog原代码。 详细介绍了流水线的设计代码-Branch prediction with the MIPS pipeline verilog source code. Details of pipeline design code
Platform: | Size: 17408 | Author: 张鹤 | Hits:

[VHDL-FPGA-Verilog] waterline_adder

Description: 这是一个用Verilog编写的四级流水线加法器-This is a Verilog prepared with four pipeline adder
Platform: | Size: 1024 | Author: 伊莲幽梦 | Hits:

[Windows Develop] CPU_verilog

Description: 一个4级流水线CPU的verilog代码，供参考学习使用，有些语句不能综合，可以通过它学习CPU的工作原理。-A 4-stage pipeline CPU' s verilog code, learning to use for reference, some statements can not be integrated, you can learn from CPU through its works.
Platform: | Size: 63488 | Author: xq | Hits:

[VHDL-FPGA-Verilog] arm7

Description: ARM7 VERILOG源码，非常精简，3级流水线-ARM7 VERILOG source code, very streamlined, 3-stage pipeline
Platform: | Size: 173056 | Author: hcq | Hits:

[VHDL-FPGA-Verilog] PIPE_LINING_CPU_TEAM_24

Description: 采用Quatus II编译环境，使用Verilog HDL语言编写实现了五段流水线CPU。 能够完成以下二十二条指令（均不考虑虚拟地址和Cache，并且默认为小端方式）： add rd,rs,rt addu rd,rs,rt addi rt,rs,imm addiu rt,rs,imm sub rd,rs,rt subu rd,rs,rt nor rd,rs,rt xori rt,rs,imm clo rd,rs clz rd,rs slt rd,rs,rt sltu rd,rs,rt slti rt,rs,imm sltiu rt,rs,imm sllv rd,rt,rs sra rd,rt,shamt blez rs,imm j target lwl rt,offset(base) lwl rt,offset(base) lw rt,imm(rs) sw rt,imm(rs) 在本设计中，采取非常良好的模块化编程风格，共分十三个主要模块PIPE_LINING_CPU_TEAM_24.v为顶层实体文件，对应为PIPE_LINING_CPU_TEAM_24模块作为顶层实体模块，如下： ifetch.v、regdec.v、exec.v、mem.v、wr.v分别实现五个流水段； cpuctr.v用于产生CPU控制信号； ALU.v用于对操作数进行相应指令的运算并输出结果； DM.v数据存储器 IM.v指令存储器 datareg.v数据寄存器堆 extender.v位扩展 yiwei_32bits.v 实现32位四种移位方式的移位器 在顶层实体中，调用ifetch.v、regdec.v、exec.v、mem.v、wr.v这五个模块就实现了流水线CPU。顶层模块的结构清晰明了。对于学习verilog编程非常有用- Quatus II compiled by the environment, using Verilog HDL language to achieve a five-stage pipeline CPU. To complete the following 22 commands (not considering the virtual address and Cache, and the default mode for the small end): add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt subu rd, rs, rt nor rd, rs, rt xori rt, rs, imm clo rd, rs clz rd, rs slt rd, rs, rt sltu rd, rs, rt slti rt, rs, imm sltiu rt, rs, imm sllv rd, rt, rs sra rd, rt, shamt blez rs, imm j target lwl rt, offset (base) lwl rt, offset (base) lw rt, imm (rs) sw rt, imm (rs) In this design, take a very good modular programming style, is divided into 13 main modules PIPE_LINING_CPU_TEAM_24.v for the top-level entity file, the corresponding module as a top-level entity for the PIPE_LINING_CPU_TEAM_24 modules, as follows: ifetch.v, regdec.v, exec.v, mem.v, wr.v water were to achieve the five paragraph cpuctr.v used to generate CPU control signal ALU.v accordingly
Platform: | Size: 4946944 | Author: 石 | Hits:

[VHDL-FPGA-Verilog] PipelineCPU

Description: 用Verilog实现一个简单的流水线CPU，并运行一个Quicksort程序。这是Berkley，eecs系的计算机系统结构课程实验的实验三。-This file is written in Verilog to achieve a simple pipeline CPU, which can run a Quicksort program.
Platform: | Size: 28672 | Author: Matgek | Hits:

[VHDL-FPGA-Verilog] cordic-verilog

Description: 用Verilog写的cordic相位鉴别，采用8级的流水线的硬件设计-Written using Verilog cordic phase identification, using 8-level hardware design of the pipeline
Platform: | Size: 1024 | Author: 朱子翰 | Hits:

[VHDL-FPGA-Verilog] PipeLine.tar

Description: Verilog实现MIPS五段流水线，22条指令（基本算术、移位和load、store指令），模块化设计，含注释-Verilog realization of five-stage pipeline MIPS 22 instructions (basic arithmetic, shift, and load, store instructions), modular design, with annotations
Platform: | Size: 2929664 | Author: czl | Hits:

[VHDL-FPGA-Verilog] pipelined-mips-cpu

Description: 用verilog语言描述了MIPS的5级流水线。-Language described by verilog MIPS 5-stage pipeline.
Platform: | Size: 171008 | Author: jack chen | Hits:

[VHDL-FPGA-Verilog] cpu

Description: 5 stage pipeline CPU, verilog HDL code-5 stage pipeline CPU
Platform: | Size: 2048 | Author: dylan | Hits:

[VHDL-FPGA-Verilog] pipelALU

Description: pipeline ALU verilog code
Platform: | Size: 2048 | Author: holyhi | Hits:

[VHDL-FPGA-Verilog] Conversion

Description: pipeline test in verilog
Platform: | Size: 1024 | Author: buni | Hits:

[VHDL-FPGA-Verilog] CPU-Pipeline

Description: 五级流水线的CPU的工程文件，在vivado上用verilog语言实现，包括串口，可进行简单的数学加法运算。(Five-stage pipeline CPU project files, including the serial port. vivado Verilog language. This CPU can do simple mathematical addition.)
Platform: | Size: 14336 | Author: Si Cheng | Hits:

[Other] 1

Description: 针对矿浆管道工况调整给泄漏检测带来的干扰，准确提取泄漏信号的特征量是降低泄漏误报、漏报的关键。为此，提出了一种基于经验模态分解（EMD）、Hilbert能量谱与变量预测模型（VPMCD）相结合的泄漏检测方法。该方法首先将压力信号分解成若干个固有模态函数（IMF）之和，然后将IMF分量进行Hilbert变换得到局部Hilbert能量谱，依据能量分布的标准差选择最能准确反映矿浆管道运行工况的局部能量谱作为特征值向量，最后通过VPMCD分类器建立泄漏识别模型。将该方法应用于泄漏检测中，实验结果表明，矿浆管道在正常运行、泄漏和工况调整状态下，识别率达到95%，并综合分析流量信号，提高了泄漏检测精度。(According to the interference to leak detection of mineral slurry pipeline caused by work condition adjustment,effectively extracting the characteristics of leak signal is the key to reduce the leakage of the false negatives and false positives.In this paper,a leak detection method based on EMD and VPMCD is proposed. In this method,the pressure signals are decomposed into several IMF components, and then take local Hilbert energy spectrum which most accurately reflect the pipeline operation conditions as feature values, Finally the leak identification model is established by VPMCD classifier.When the method is applied to the leak detection,the experimental results show that under the conditions of normal operation,leakage and work condition adjustment, the recognition rate of the mineral slurry pipeline reaches 95%,and by comprehensively analyzing the flow signals, it also improves the accuracy of leak detection.)
Platform: | Size: 4096 | Author: M-min | Hits:
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